Vedhas Pandit Email & Phone Number
Researcher @ Helmholtz-Zentrum Dresden-Rossendorf (HZDR)
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Vedhas Pandit Location
- Dresden, SN, DE
Vedhas Pandit Work
- 2024 -now Researcher @
- 2023 -2024 Head of AI Operations @
- 2021 -2023 Data Scientist and Machine Learning Engineer @
- 2020 -2022 Founder and Researcher @ Hobby-yard/sandbox (the word 'startup' is too strong a claim :) )
- 2017 -2021 Research staff (Wissenschaftlicher Mitarbeiter) and a Ph.D. candidate @
- 2019 -2020 Senior AI Developer @
- 2015 -2017 Research staff and PhD candidate (finished at Uni-Augsburg) @
- 2013 -2014 Research Staff @
- 2011 -2013 Graphics Hardware Engineer @
- 2008 -2011 Graduate Researcher @
Vedhas Pandit Education
- University of Augsburg
Doctor of Philosophy (Artificial Intelligence)
2017-2021 - Arizona State University
Master of Science (Electrical Engineering)
2008-2010 - COEP Technological University
Bachelor of Technology (Electrical Engineering)
2004-2008 - Ramnarain Ruia College
H.S.C. (Computer Science)
2002-2004 - Balmohan Vidyamandir 1990-2002
- Universität Passau
Doctor of Philosophy (Ph.D.) *candidate* // then continued at Uni-Augsburg (Complex and Intelligent Engineering Systems)
2015
Vedhas Pandit Skills
- Mathematics
- Schematic
- Field Programmable Gate Arrays Fpga
- Functional Verification
- Perl
- Matlab
- TensorFlow
- Analog
- Floor Cleaning
- Mentoring
- Formal Verification
- Audio Engineering
- GDS
- Software Development Tools
- Tflearn
- Features
- DFX
- Robotics
- Simulations
- Design
- Mos
- Coaching
- Digital Signal Processors
- Mathematica
- Analog Circuits
- Silvaco
- Aldec
- Keys
- Drift
- Leadership
- Physics
- Linux
- Algorithms
- Assembly Language
- SPICE
- Reliability
- Acoustics
- Data Validation
- Robot
- Timing
- Layout
- Xilinx
- Engineering
- Circuits
- Semiconductor Process Technology
- Mask
- Rom
- Device Modeling
- Ecos
- Computer Programming
- Mixed Signal
- LVS
- DSP
- Soi
- SystemVerilog
- DRC
- Output
- Research
- Digital Signal
- Hardware
- JTAG
- Vehicles
- AutoCAD
- Amplifiers
- C
- MDS
- Specs
- Sensors
- Intel
- ASIC
- Modeling
- Verilog
- Music
- Scrap
- Circuit Design
- Characterization
- Signal Processing
- RV
- FPGA
- Checks
- EDA
- Digital Signal Processing
- Tft
- Tape
- Pspice
- Static Timing Analysis
- Semiconductor Process
- Presentations
- Device Design
- Pattern Recognition
- Project Delivery
- Semiconductor Device
- Packaging
- Milestones
- Bert
- Cadence Virtuoso
- Logic Synthesis
- Resources
- Teaching
- Graphics
- Technical Leadership
- Flux
- Microcontrollers
- Materials
- Cadence
- Software
- Commitments
- Video
- Proposition
- TI DSPs
- Algorithm Design
- CMOS
- Analytical Skill
- Rtl
- Theory
- C++
- Data Compression
- Python
- Semiconductors
- Fft
- TCAD
- Software Development
- Vlsi Design
- Architecture
- Automation
- Programming
- Machine Learning
- Deep Learning
- R
- Data Analysis
- Data Science
- Field Programmable Gate Arrays
Vedhas Pandit Summary
- Vedhas Pandit, based in Dresden, SN, DE, is currently a Researcher at Helmholtz-Zentrum Dresden-Rossendorf (HZDR). Vedhas Pandit brings experience from previous roles at Advancing Individual Networks (AIN), Amdocs, Hobby-yard/sandbox (the word 'startup' is too strong a claim :) ) and University of Augsburg. Vedhas Pandit holds a 2017 - 2021 Doctor of Philosophy in Artificial Intelligence @ University of Augsburg. With a robust skill set that includes Mathematics, Schematic, Field Programmable Gate Arrays Fpga, Functional Verification, Perl and more. Vedhas Pandit has 1 emails and 1 mobile phone numbers on RocketReach.
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