Varun Patel Email & Phone Number
Senior Hardware Engineer @ NVIDIA
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Varun Patel Location
- Santa Clara, CA, US
Varun Patel Work
- 2014 -now Senior Hardware Engineer @
- 2014 -2014 Verification Consultant @
- 2010 -2014 Member of Technical Staff - ASIC Division @
- 2008 -2009 Teaching Associate @
- 2008 -2008 Student Assistant @
- 2006 -2007 Embedded Intern @
Varun Patel Education
- California State University-Sacramento
Master’s Degree (Electrical Engineering; VLSI and Computer Engineering)
2007-2010 - L.D. College of Engineering
Bachelors (Electrical Engineering; Electronics & Communications)
2003-2007
Varun Patel Skills
- Verilog
- SystemVerilog
- Static Timing Analysis
- Logic Design
- ModelSim
- Perl
- Unix
- VCS
- CMOS
- Caching
- Functional Verification
- Ethernet
- USB3.0
- Xilinx ISE
- EDA
- FPGA
- Veritas Cluster Server
- VLSI
- VHDL
- ASIC
- Computer Architecture
- DFT
- Debugging
- Open Verification Methodology
- PCIe
- Application-Specific Integrated Circuits (ASIC)
- Very-Large-Scale Integration (VLSI)
- Universal Verification Methodology (UVM)
- System on a Chip (SoC)
- Linux
- RTL Design
- Open Verification
- Application Specific Integrated Circuits Asic
- Manufacturing
- Very Large Scale Integration Vlsi
- Verification
- Application Specific Integrated Circuits
- Very Large Scale Integration
Varun Patel Summary
- Varun Patel, based in Santa Clara, CA, US, is currently a Senior Hardware Engineer at NVIDIA. Varun Patel brings experience from previous roles at Broadcom, Sibridge Technologies and California State University, Sacramento. Varun Patel holds a 2007 - 2010 Master’s Degree in Electrical Engineering; VLSI and Computer Engineering @ California State University-Sacramento. With a robust skill set that includes Verilog, SystemVerilog, Static Timing Analysis, Logic Design, ModelSim and more. Varun Patel has 2 emails and 1 mobile phone numbers on RocketReach.
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