Van Thai Email
Senior FPGA Design, Verification, and Validation Engineer @ Accedian
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Van Thai Location
- Montreal, QC, CA
Van Thai Work
- 2016 -now Senior FPGA Design, Verification, and Validation Engineer @
- 2009 -2015 Staff ASIC Design and Implementation Engineer @
- 2008 -2009 Senior DFT Consultant @ XtremeEDA
- 2000 -2008 Product Design Engineer @
Van Thai Education
- McGill University
BEng (Computer Engineering)
1995-2000 - Dawson College
Pure & Applied Science
1993-1995
Van Thai Skills
- RTL design
- Timing Closure
- ASIC
- Static Timing Analysis
- Functional Verification
- DFT
- Formal Verification
Van Thai Summary
- Van Thai, based in Montreal, QC, CA, is currently a Senior FPGA Design, Verification, and Validation Engineer at Accedian is now part of Cisco. Van Thai brings experience from previous roles at PMC-Sierra Inc, XtremeEDA and PMC-Sierra, Inc. Van Thai holds a 1995 - 2000 BEng in Computer Engineering @ McGill University. With a robust skill set that includes RTL design, Timing Closure, ASIC, Static Timing Analysis, Functional Verification and more. Van Thai has 1 emails on RocketReach.
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