Vaibhav Agrawal's Location

Austin, TX, US

Vaibhav Agrawal's Work

  • Formal Verification @ Arm
  • Manager & Team Lead, Front End Design & Verification Methodology/CAD for Atom CPUs and SoCs @ Intel Corporation
  • Formal Verification @ Arm
  • Manager and Team Lead, Front End Design and Verification Methodology and Cad for Atom Cpus and Socs @ Intel Corporation
  • Front End Design and Verification Methodology and Automation Engineer for Atom Cpus and Socs @ Intel Corporation
  • Formal Verification Engineer for Pentium Iv Class Design @ Intel Corporation
  • Design Verification Intern at M-Core Technology Center @ Motor X
  • Design Engineer @ Texas Instruments

Vaibhav Agrawal's Education

  • University of Texas

    Master of Science in Electrical Engineering (Computer Engineering)

    1998 - 2000
  • Indian Institute of Technology

    Bachelor of Technology (Electrical Engineering)

    1992 - 1996

Vaibhav Agrawal's Skills

  • Functional Verification
  • Verilog
  • Processors
  • ASIC
  • SystemVerilog
  • Formal Verification
  • VLSI
  • Logic Design
  • IC
  • RTL coding

Vaibhav Agrawal's Summary

Vaibhav Agrawal, based in Austin, TX, US, is currently a Formal Verification at ARM, bringing experience from previous roles at Intel Corporation and Arm. Vaibhav Agrawal holds a 1998 - 2000 Master of Science in Electrical Engineering in Computer Engineering @ University of Texas. With a robust skill set that includes Functional Verification, Verilog, Processors, ASIC, SystemVerilog and more, Vaibhav Agrawal contributes valuable insights to the industry. Vaibhav Agrawal has 2 emails and 1 mobile phone number on RocketReach.

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