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Ujas Patel Location
Dallas, TX, US
Ujas Patel Work
2020 -now Power UPF methodolody engineer @
2017 -2020 Component design engineer @
2015 -2016 Graduate Student Researcher, Texas Analog Center of Excellence(TxACE) @
2014 -2016 Graduate Student @
2014 -2014 Student Worker @
Ujas Patel Education
The University of Texas at Dallas
Master of Science (MS) (Electrical Engineering)
2014-2015
L.D. College of Engineering
Bachelor of Engineering (B.E.) (Electronics and Communication Engineering)
2009-2013
Ujas Patel Skills
AWR Microwave Office
RF
Computer Architecture
Cadence Virtuoso
C
Analog Circuit Design
SPICE
Logic Synthesis
HSPICE
Perl
Matlab
Analog
ASIC
Mixed Signal Ic Design
Xilinx ISE
VLSI
Verilog
Integrated Circuit Design
Microcontrollers
Place And Route
Xilinx
Cadence
Engineering
Circuit Design
Microsoft Office
Mixed Signal
CMOS
Testing
FPGA
SoC
RTL coding
VHDL
ModelSim
C++
Synopsys Primetime
SystemVerilog
Synopsys tools
Semiconductors
Physical Design
Simulations
Pspice
Static Timing Analysis
Low Power Design
Very Large Scale Integration Vlsi
Digital Circuit Design
Very Large Scale Integration
Ujas Patel Summary
Ujas Patel, based in Dallas, TX, US, is currently a Power UPF methodolody engineer at Apple. Ujas Patel brings experience from previous roles at Intel Corporation and University of Texas at Dallas. Ujas Patel holds a 2014 - 2015 Master of Science (MS) in Electrical Engineering @ The University of Texas at Dallas. With a robust skill set that includes AWR Microwave Office, RF, Computer Architecture, Cadence Virtuoso, C and more. Ujas Patel has 2 emails and 3 mobile phone numbers on RocketReach.
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