Tuo Wang Email & Phone Number
Member of Technical Staff @ OpenAI
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Tuo Wang Location
- San Jose, CA, US
Tuo Wang Work
- Member of Technical Staff @ (November 2024 - Present)
- ASIC and FPGA Engineer @ (March 2019 - November 2024)
- Senior GPU Verification Engineer @ (August 2018 - March 2019)
- Verification Lead @ (September 2017 - August 2018)
- Senior Engineer @ (June 2015 - September 2017)
- Senior Verification Engineer @ (June 2013 - June 2015)
- Marster Co-op @ Cypress Semiconductor (February 2013 - May 2013)
Tuo Wang Education
- University of Southern California
Master of Science (MS) (Electrical Engineering-VLSI)
2011-2013 - Dalian University of Technology
BS (Electrical and Electronics Engineering)
2007-2011
Tuo Wang Skills
- ASIC design
- C
- Cadence Conformal LEC
- Cadence Virtuoso
- Computer Architecture
- Coverage
- ModelSim
- NC-Verilog
- Perl
- Power Aware Verification
- RTL design
- Static Timing Analysis
- Synopsys Design Compiler
- Synopsys Primetime
- Synopsys VCS
- System Verilog
- UPF
- UVM
- VMM
- Verilog
- SQL
- Requirements Analysis
- ASIC
- Project Management
- PowerPoint
- Microsoft Office
- Nc Verilog
Tuo Wang Summary
- Tuo Wang, based in San Jose, CA, US, is currently a Member of Technical Staff at OpenAI. Tuo Wang brings experience from previous roles at Facebook, NVIDIA, NovuMind Inc. and Seagate Technology. Tuo Wang holds a 2011 - 2013 Master of Science (MS) in Electrical Engineering-VLSI @ University of Southern California. With a robust skill set that includes ASIC design, C, Cadence Conformal LEC, Cadence Virtuoso, Computer Architecture and more. Tuo Wang has 2 emails and 5 mobile phone numbers on RocketReach.
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