Tuan Van Tran's Location
San Martin, CA, US
Tuan Van Tran's Work
- ic layout engineer @ Altera
- IC Layout Mask Designer and Contractor @ Intel Corporation
- ic layout mask designer contractor @ Altera
- IC layout Mask Designer @ Intel Corporation
Tuan Van Tran's Education
- San Jose State University
Bachelor of Engineering (B.E.) (Electrical and Electronics Engineering)
Tuan Van Tran's Skills
- Io and Mix Signal Layouts
- SoC
- Analog
- CMOS
- Debugging
- Mixed Signal
- Physical Design
- LVS
- DRC
- Processors
Tuan Van Tran's Summary
Tuan van Tran, based in San Martin, CA, US, is currently a ic layout engineer at altera corp, bringing experience from previous roles at Intel Corporation and Altera. Tuan van Tran holds a Bachelor of Engineering (B.E.) in Electrical and Electronics Engineering @ San Jose State University. With a robust skill set that includes Io and Mix Signal Layouts, SoC, Analog, CMOS, Debugging and more, Tuan van Tran contributes valuable insights to the industry. Tuan van Tran has 1 email on RocketReach.
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