Tom Stanway-Mayers Email
Senior Analogue IC Design Engineer @ Intrinsic
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Tom Stanway-Mayers Location
- Cambridge, GB
Tom Stanway-Mayers Work
- 2025 -now Senior Analogue IC Design Engineer @
- 2024 -2025 Senior Staff Analog IC Design Engineer @
- 2021 -2023 Senior Member of Technical Staff @
- 2014 -2021 Senior Silicon Engineer @
- 2008 -2014 Hardware Design Engineer @
Tom Stanway-Mayers Education
- Imperial College London
Master of Science (MSc) (Analogue & Digital Integrated Circuit Design)
2007-2008 - Imperial College London
Bachelor of Engineering (BEng) (Information Systems Engineering)
2004-2007
Tom Stanway-Mayers Skills
- PADS Layout
- Hardware Architecture
- Linux
- C
- Consumer Electronics
- Debugging
- Assembly Language
- Graphic Design
- ARM
- Processors
- ASIC
- Cisco
- Cadence
- Engineering
- Tandberg
- Java
- Embedded Systems
- Codian
- FPGA
- VHDL
- Pads Logic
- C/C++ STL
- Design
- Hardware
- X86
- Risc V
- Verilog
- Asic Design
Tom Stanway-Mayers Summary
- Tom Stanway-Mayers, based in Cambridge, GB, is currently a Senior Analogue IC Design Engineer at Intrinsic. Tom Stanway-Mayers brings experience from previous roles at Lightmatter, Rivos Inc., Google and CISCO SYSTEMS (USA) PTE. LTD. Tom Stanway-Mayers holds a 2007 - 2008 Master of Science (MSc) in Analogue & Digital Integrated Circuit Design @ Imperial College London. With a robust skill set that includes PADS Layout, Hardware Architecture, Linux, C, Consumer Electronics and more. Tom Stanway-Mayers has 2 emails on RocketReach.
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Tom Stanway-Mayers
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