Tom Email & Phone Number
Design Verification Engineer @ Eridu AI
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Tom Location
- Santa Clara, CA, US
Tom Work
- 2025 -now Design Verification Engineer @
- 2018 -2025 Verification Engineer @
- 2017 -2018 Technical Manager @ Yangtze Memory Technologies, Inc.
- 2015 -2017 Senior Design Verification Engineer @
- 2015 -2015 Design Verification Engineer @
- 2014 -2015 Verification Engineer Intern @
- 2014 -2015 Master in Computer Science @
- 2014 -2014 Senior Media Systems Assistant @
- 2012 -2013 Senior Verification Engineer @
- 2010 -2012 Verification Engineer @
- 2009 -2010 Verification Engineer @
Tom Education
- Santa Clara University
Master's Degree (Computer Science)
2014-2015 - Huazhong University of Science and Technology
Master's degree (Software Engineering)
2007-2009
Tom Skills
- SystemVerilog
- Verilog
- UVM
- VMM
- SVA
- Assertion Based Verification
- VHDL
- Perl
- Python
- Machine Learning
- C++
- VCS
- Verdi
- NCSIM
- Semiconductors
- GNU Make
- GNU Compiler Collection (GCC)
- Processors
- Makefile
- SoC
- FPGA
- Functional Verification
- Computer Architecture
- IP Addressing
- C
- Top level verification
- IP verification
- ASIC
- Java
- JavaScript
- Testing
- Xilinx Vivado
- Linux
- Batch Files
- System C
- Assembling
- ARM
- Bash
- Emacs
- Vim
- OpenCV
- RTL Design
- Matlab
- TexLive
- DPI-C
- MIPS
- Functional Coverage
- NAND Flash
- SimVision
- Data Analysis
- Information Security
- Dpi C
- VLSI
- Software
- TCL
- Developers
- ModelSim
- Gnu Compiler Collection Gcc
- CSS
- HTML5
- Gnu Compiler Collection
Tom Summary
- Tom, based in Santa Clara, CA, US, is currently a Design Verification Engineer at Eridu AI. Tom brings experience from previous roles at PetaIO, Yangtze Memory Technologies, Inc., SanDisk, a Western Digital Brand and Esencia Technologies Inc.. Tom holds a 2014 - 2015 Master's Degree in Computer Science @ Santa Clara University. With a robust skill set that includes SystemVerilog, Verilog, UVM, VMM, SVA and more. Tom has 2 emails and 2 mobile phone numbers on RocketReach.
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