Tin N. Email & Phone Number
FPGA Design Engineer @ Apex Compute
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Tin N. Location
- San Jose, CA, US
Tin N. Work
- FPGA Design Engineer @ (May 2025 - Present)
Tin N. Skills
- Altium Designer
- Assembly Language
- Automatic Test Pattern Generation (ATPG)
- BIST
- Bash
- Boundry Scan
- C (Programming Language)
- C++
- Cadence
- Cadence Encounter
- Cadence Genus
- Cadence Schematic Capture
- Cadence Spectre
- Cadence Virtuoso
- Calculus
- Computer Hardware Troubleshooting
- DFT
- DFT Compiler
- Design Rule Checking (DRC)
- Eagle PCB
- FreeRTOS
- Gitlab
- Layout Versus Schematic (LVS)
- Libero
- Linux
- MIPS Assembly
- MIPS Instruction Set
- MLP
- MathCAD
- ModelSim
- NC-Verilog
- Physics
- Powershell
- Programming
- Programming Languages
- Python (Programming Language)
- RTL Coding
- RTL Design
- SUE Schematic
- SciPy
- Seaborn
- Simvision
- SketchUp
- Synopsys Design Compiler
- SystemVerilog
- TMAX
- TensorFlow
- Unity
- Verilog
- Visual Studio
- Vitis
- Vitis HLS
- Vitis IDE
- Wave Solder
- Xilinx Vivado
Tin N. Summary
- Tin N., based in San Jose, CA, US, is currently a FPGA Design Engineer at Apex Compute. With a robust skill set that includes Altium Designer, Assembly Language, Automatic Test Pattern Generation (ATPG), BIST, Bash and more. Tin N. has 1 mobile phone numbers on RocketReach.
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