Tim Low Email & Phone Number
Solutions Director @ Cadence Design Systems
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Tim Low Location
- Beaverton, OR, US
Tim Low Work
- 2024 - now Solutions Director @
- 2019 - 2024 Architect @
- 2015 - 2019 Sr Platform Architect and Technical Design Lead, Data Center Group @
- 2007 - 2015 Analog Mixed Signal Technical Lead @
- 1994 - 2007 Sr Design Engineer @
Tim Low Education
- Oregon State University
Tim Low Skills
- Verilog
- Mixed Signal
- SystemVerilog
- PLL
- Analog
- SoC
- DFT
- Processors
- Verilog-A
- PCIe
- ASIC
- Analog Circuit Design
- RTL design
- Circuit Design
- Functional Verification
- Cadence Virtuoso
- ModelSim
- Perl
- DDR
- Debugging
- Computer Architecture
- Microprocessors
- Spectre
- Matlab
- C
- Cadence
- VLSI
- Power Management
- Intel
- Low-power Design
- CMOS
- IC
- Physical Design
- Phase-Locked Loop (PLL)
- Microsoft Office
- Data Validation
- Management
- Low Power Design
- Agile Methodologies
- SQL
- Public Speaking
- Phase Locked Loop Pll
- Architecture
- Development
- Validation
- Phase Locked Loop
Tim Low Summary
- Tim Low, based in Beaverton, OR, US, is currently a Solutions Director at Cadence Design Systems. Tim Low brings experience from previous roles at Cadence Design Systems and Intel Corporation. Tim Low holds a Oregon State University. With a robust skill set that includes Verilog, Mixed Signal, SystemVerilog, PLL, Analog and more. Tim Low has 2 emails and 2 mobile phone numbers on RocketReach.
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