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Tim Lantz Location
Scotts Valley, CA, US
Tim Lantz Work
Senior Principal Engineer @ (September 2025 - Present)
Principal Engineer @ (March 2021 - October 2025)
Senior SoC Physical Design Lead, Custom CPU Product Development @ (January 2017 - March 2021)
Technical Leader @ (January 2005 - January 2017)
Hardware Engineer @ (January 2001 - January 2005)
Consultant @ Monterey Design Systems (January 2003 - January 2003)
Hardware Engineer @ (January 1998 - January 2001)
Hardware Engineer @ Silicon Engineering Inc. (SEI) (January 1996 - January 1998)
Tim Lantz Education
University of California, Santa Cruz 1992-1996
Tim Lantz Skills
ARM
ASIC
Application-Specific Integrated Circuits (ASIC)
Artificial Intelligence for Business
Business Strategy
Computer Architecture
Computer Hardware
DFT
Debugging
Digital IC Design
Digital Signal Processors
EDA
FPGA
Floorplanning
Formal Verification
Functional Verification
Hardware
Hardware Architecture
IC
Integrated Circuit Design
Integrated Circuits (IC)
Logic Design
Logic Synthesis
Low-power Design
Microprocessors
NCSim
PCIe
Perl
Physical Design
Primetime
Processors
RTL Design
RTL coding
SoC
Static Timing Analysis
SystemVerilog
TCL
Timing Closure
UVM
VHDL
VLSI
VMM
Verilog
Very-Large-Scale Integration (VLSI)
Integrated Circuits Ic
Application Specific Integrated Circuits Asic
Low Power Design
Very Large Scale Integration Vlsi
Application Specific Integrated Circuits
Integrated Circuits
Very Large Scale Integration
Tim Lantz Summary
Tim Lantz, based in Scotts Valley, CA, US, is currently a Senior Principal Engineer at Tenstorrent. Tim Lantz brings experience from previous roles at Intel Corporation, Cisco Systems and Tau Networks. Tim Lantz holds a 1992 - 1996 University of California, Santa Cruz. With a robust skill set that includes ARM, ASIC, Application-Specific Integrated Circuits (ASIC), Artificial Intelligence for Business, Business Strategy and more. Tim Lantz has 1 emails and 1 mobile phone numbers on RocketReach.
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