Tim Lacey Email & Phone Number
Sr. Design Director @ Infineon Technologies
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Tim Lacey Location
- Colorado Springs, CO, US
Tim Lacey Work
- Sr. Design Director @ (March 2015 - Present)
- Sr. Design Director @ (July 2005 - January 2010)
- Design Director @ (July 1998 - July 2005)
- Design Manager @ (January 1992 - January 1998)
- Program Manager @ (January 1989 - January 1992)
- Design @ (January 1987 - January 1989)
Tim Lacey Education
- University of Wisconsin - Madison
(Computer Science)
- Stanford University
(Electrical Engineering)
Tim Lacey Skills
- ASIC
- Analog
- Analog Circuit Design
- BiCMOS
- CMOS
- Cadence
- Cadence Virtuoso
- Circuit Design
- Clock Tree Synthesis
- Cross-functional Team Leadership
- DFT
- DRC
- EDA
- Engineering Management
- FPGA
- Floorplanning
- Functional Verification
- Hardware Architecture
- IC
- Integrated Circuit Design
- LVS
- Logic Design
- Low-power Design
- Microelectronics
- Mixed Signal
- PLL
- Physical Design
- Physical Verification
- Power Management
- Primetime
- Problem Solving
- Processors
- Product Development
- Program Management
- RTL coding
- RTL design
- SERDES
- SRAM
- Semiconductor Industry
- Semiconductors
- Signal Integrity
- Silicon
- SoC
- Spectre
- Static Timing Analysis
- SystemVerilog
- Timing Closure
- USB
- VLSI
- Verilog
Tim Lacey Summary
- Tim Lacey, based in Colorado Springs, CO, US, is currently a Sr. Design Director at Infineon Technologies. Tim Lacey brings experience from previous roles at Cypress Semiconductor. Tim Lacey holds a University of Wisconsin - Madison. With a robust skill set that includes ASIC, Analog, Analog Circuit Design, BiCMOS, CMOS and more. Tim Lacey has 1 emails and 1 mobile phone numbers on RocketReach.
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