Thomas Severin Email
Engineerin Manager - Digital Design and DV @ Apple
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Thomas Severin Location
- Bavaria, Germany
Thomas Severin Work
- 2019 -now Engineerin Manager - Digital Design and DV @
- 2018 -2019 Engineering Manager @
- 2015 -2018 Senior Digital Design and Verification Engineer @
- 2012 -2014 Senior Design Engineer - ASIC and FPGA @ metaio GmbH
- 2009 -2012 Senior Design Engineer - ASIC and FPGA @
- 2008 -2009 SOC Product Development Engineer @
- 2005 -2008 ASIC Designer, Deputy Chief of ASIC Design Methodology Department @
- 2003 -2005 ASIC Designer @
- 1999 -2003 ASIC Designer @ SecWare Technologies AG
Thomas Severin Education
- Technical University Berlin
Thomas Severin Skills
- Memory
- Open Verification
- Field Programmable Gate Arrays Fpga
- System On A Chip Soc
- Logic Synthesis
- Functional Verification
- OVM
- RTL design
- ARM
- Technical Project
- UVM
- ASIC
- IPSec
- IP
- Profinet
- Verilog
- Integrated Circuit Design
- Formal Verification
- ARM Architecture
- Technical Project Leadership
- Xilinx
- TCP/IP
- TCL
- Ethernet
- Integrated Circuit
- Encryption
- Application Specific Integrated Circuits Asic
- MIPS
- FPGA
- SoC
- Open Verification Methodology
- RTL coding
- VHDL
- EDA
- Assertions
- Universal Verification Methodology Uvm
- Altera
- SystemVerilog
- Design
- Project Management
- PCI Standards
- Static Timing Analysis
- Integration
- Verification
- Verification Specialist
- IC
- Field Programmable Gate Arrays
- Application Specific Integrated Circuits
- Universal Verification Methodology
- System on a Chip
Thomas Severin Summary
- Thomas Severin, based in Bavaria, Germany, is currently a Engineerin Manager - Digital Design and DV at Apple. Thomas Severin brings experience from previous roles at Intel Corporation, metaio GmbH and KUNBUS GmbH. Thomas Severin holds a Technical University Berlin. With a robust skill set that includes Memory, Open Verification, Field Programmable Gate Arrays Fpga, System On A Chip Soc, Logic Synthesis and more. Thomas Severin has 1 emails on RocketReach.
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