Thierry Besson Email & Phone Number
Principal Engineer @ Zero ASIC
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Thierry Besson Location
- Boston, MA, US
Thierry Besson Work
- 2025 -now Principal Engineer @
- 2021 -2025 Director of Software and EDA Synthesis @ EuroDev / Rapid Silicon (Los Gatos, CA, USA)
- 2017 -2021 Logic Synthesis Architect @
- 2015 -2017 Principal Engineer @
- 2012 -2014 Principal Software Engineer @
- 2004 -2011 Principal Engineer @
- 2002 -2004 Senior Staff Engineer @
- 2000 -2002 Senior Staff Engineer @
- 1999 -2000 Staff Engineer @
- 1998 -1998 Staff Engineer @ interHdl
- 1997 -1998 Senior Software Engineer @
- 1996 -1998 Software Engineer @ Compass Design Automation / Avant! Corp.
- 1994 -1996 Software Engineer @ Innovative Synthesis Technologies
Thierry Besson Education
- INP Grenoble & UC Berkeley
Ph.D. (Thesis :"BDDs and applications" with Pr. G. Saucier (CSI Laboratory, INP Grenoble) & Pr. R.K. Brayton (UC Berkeley, EECS department))
1990-1996 - University of California, Berkeley
Ph.D student at EECS department (UC Berkeley, CA, USA with Pr. R.K.Brayton)
1991-1994 - National School of Computer Science and Applied Mathematics of Grenoble
Ingénieur ENSIMAG (groupe ENSI (Ecoles Nationales Supérieures d'Ingénieurs), computer science (Software Engineering & Artificial Intelligence))
1987-1990
Thierry Besson Skills
- SystemVerilog
- Physical Design
- ASIC
- Static Timing Analysis
- Application Specific Integrated Circuits Asic
- SoC
- Verilog
- Formal Verification
- Algorithms
- VLSI
- EDA
- VHDL
- Debugging
- TCL
- Logic Synthesis
- Functional Verification
- RTL design
- Application Specific Integrated Circuits
Thierry Besson Summary
- Thierry Besson, based in Boston, MA, US, is currently a Principal Engineer at Zero ASIC. Thierry Besson brings experience from previous roles at EuroDev / Rapid Silicon (Los Gatos, CA, USA), NanoXplore SAS, Mentor Graphics and Cadence Design Systems. Thierry Besson holds a 1990 - 1996 Ph.D. in Thesis :"BDDs and applications" with Pr. G. Saucier (CSI Laboratory, INP Grenoble) & Pr. R.K. Brayton (UC Berkeley, EECS department) @ INP Grenoble & UC Berkeley. With a robust skill set that includes SystemVerilog, Physical Design, ASIC, Static Timing Analysis, Application Specific Integrated Circuits Asic and more. Thierry Besson has 4 emails on RocketReach.
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