Ph.D student at EECS department, UC Berkeley, CA, USA with Pr. R.K.Brayton
1991
-
1994
National School of Computer Science and Applied Mathematics of Grenoble
Ingénieur ENSIMAG, groupe ENSI (Ecoles Nationales Supérieures d'Ingénieurs) (computer science (Software Engineering & Artificial Intelligence))
1987
-
1990
Thierry Besson Skills
SystemVerilog
Physical Design
ASIC
Static Timing Analysis
Application Specific Integrated Circuits Asic
SoC
Verilog
Formal Verification
Algorithms
VLSI
EDA
VHDL
Debugging
TCL
Logic Synthesis
Functional Verification
RTL design
Application Specific Integrated Circuits
Thierry Besson Summary
Thierry Besson, based in Boston, MA, US, is currently a Principal Engineer at Zero ASIC. Thierry Besson brings experience from previous roles at EuroDev / Rapid Silicon (Los Gatos, CA, USA), NanoXplore SAS, Mentor Graphics and Cadence Design Systems. Thierry Besson holds a 1990 - 1996 Ph.D. in Computer Science @ INP Grenoble & UC Berkeley. With a robust skill set that includes SystemVerilog, Physical Design, ASIC, Static Timing Analysis, Application Specific Integrated Circuits Asic and more. Thierry Besson has 4 emails on RocketReach.
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