Director @ Signet Design Solutions VN (January 2005 - January 2009)
Hardware Designer @ Texas Instruments (January 1997 - January 2000)
Co-op @ (January 1996 - January 1996)
Thien Phan Education
RMIT 2006-2007
University of Cincinnati
BS (Computer Engineering)
Thien Phan Skills
Physical Design
ASIC
Static Timing Analysis
Cadence Edi
Low Power Design
SoC
Verilog
VLSI
EDA
Cadence Tempus
Primetime
Timing Closure
Thien Phan Summary
Thien Phan, based in Cedar Park, TX, US, is currently a Staff Design Engineer at Silicon Laboratories, Inc.. Thien Phan brings experience from previous roles at Silicon Laboratories, Inc., AMD, Signet Design Solutions and Signet Design Solutions VN. Thien Phan holds a 2006 - 2007 RMIT. With a robust skill set that includes Physical Design, ASIC, Static Timing Analysis, Cadence Edi, Low Power Design and more. Thien Phan has 2 emails and 4 mobile phone numbers on RocketReach.
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