Thien Phan Location

Cedar Park, TX, US

Thien Phan Work

  • 2000 - 2010 Senior Design Engineer @ Signet Design Solutions
  • 2005 - 2009 Director @ Signet Design Solutions VN
  • 1997 - 2000 Hardware Designer @ Texas Instruments
  • 1996 - 1996 Co-op @ Cyrix

Thien Phan Education

  • RMIT

    2006 - 2007
  • University of Cincinnati

    BS (Computer Engineering)

Thien Phan Skills

  • Physical Design
  • ASIC
  • Static Timing Analysis
  • Cadence Edi
  • Low Power Design
  • SoC
  • Verilog
  • VLSI
  • EDA
  • Cadence Tempus

Thien Phan Summary

Thien Phan, based in Cedar Park, TX, US, is currently a Staff Design Engineer at Silicon Laboratories, Inc.. Thien Phan brings experience from previous roles at Silicon Laboratories, AMD, Signet Design Solutions and Signet Design Solutions VN. Thien Phan holds a 2006 - 2007 RMIT. With a robust skill set that includes Physical Design, ASIC, Static Timing Analysis, Cadence Edi, Low Power Design and more. Thien Phan has 2 emails and 1 mobile phone numbers on RocketReach.

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