Tero Lehtinen Email

Tero Lehtinen Email

Senior Specialist @ Nokia

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Tero Lehtinen's Location

Tampere, Pirkanmaa, Finland

Tero Lehtinen's Work

  • ASIC Designer @ VLSI Solution Oy
  • Master's Thesis @ VLSI Solution Oy
  • Summer intern @ VLSI Solution Oy

Tero Lehtinen's Education

  • Tampere University of Technology 1965-2018

    MSEE (Major: Digital And Computer Systems, Minor: Embedded Systems)

Tero Lehtinen's Skills

  • ASIC
  • VHDL
  • FPGA
  • ModelSim
  • RTL design
  • Verilog
  • Integrated Circuit Design
  • Logic Synthesis

Tero Lehtinen's Summary

Tero Lehtinen, based in Tampere, Pirkanmaa, Finland, is currently a Senior Specialist at Nokia, bringing experience from previous roles at Esju Oy, ST-Ericsson and VLSI Solution Oy. Tero Lehtinen holds a MSEE in Major: Digital And Computer Systems, Minor: Embedded Systems @ Tampere University of Technology 1965-2018. With a robust skill set that includes ASIC, VHDL, FPGA, ModelSim, RTL design and more, Tero Lehtinen contributes valuable insights to the industry. Tero Lehtinen has 1 email on RocketReach.
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