Tejaswini Ch Email
Physical Design Engineer @ INVECAS
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Tejaswini Ch Location
- Hyderabad, IN
Tejaswini Ch Work
- 2022 -now Physical Design Engineer @
- 2021 -2022 Analog Layout Engineer @
- 2021 -2021 Trainee @
Tejaswini Ch Education
- Sreenidhi Institute of Science and Technology (SNIST)
Bachelor of Technology (ECE)
2017-2021
Tejaswini Ch Skills
- Synopsys IC Compiler
- Place & Route
- TCL
- Physical Design
- Timing Closure
- Primetime
- Static Timing Analysis
- Problem Solving
- Very-Large-Scale Integration (VLSI)
- Clock Tree Synthesis
- Layout Versus Schematic (LVS)
- Floorplanning
- C (Programming Language)
- C++
- MATLAB
- Cadence Virtuoso Layout Editor
- Perl
Tejaswini Ch Summary
- Tejaswini Ch, based in Hyderabad, IN, is currently a Physical Design Engineer at INVECAS. Tejaswini Ch brings experience from previous roles at INVECAS and VEDA IIT. Tejaswini Ch holds a 2017 - 2021 Bachelor of Technology in ECE @ Sreenidhi Institute of Science and Technology (SNIST). With a robust skill set that includes Synopsys IC Compiler, Place & Route, TCL, Physical Design, Timing Closure and more. Tejaswini Ch has 1 emails on RocketReach.
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