Tejas Raval Email & Phone Number
Physical Design Engineer @ Intel Corporation
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Tejas Raval Location
- Santa Clara, CA, US
Tejas Raval Work
- 2018 -now Physical Design Engineer @
- 2015 -2018 Senior CPU Physical Design Engineer @
- 2012 -2015 CPU Physical Design Engineer @
- 2012 -2012 Teaching Assistant @ Electrical Engineering Department, California State University, Northridge
- 2009 -2009 Project Intern @ INMED Equipments Pvt. Ltd
Tejas Raval Education
- California State University-Northridge
MS Electrical (ASIC/FPGA Design)
2010-2012 - California State University, Fullerton
MS Electrical Engineering (Semiconductor physics)
2009-2010 - Sardar Vallabhbhai Patel Institute of Technology, Gujarat University
Bachelor of Science (BS) (Electrical, Electronics and Communications Engineering)
2005-2009
Tejas Raval Skills
- Verilog
- ASIC
- Matlab
- TCL
- Static Timing Analysis
- Compilers
- Formal Verification
- Physical Design
- Logic Synthesis
- Primetime
- Xilinx
- Functional Verification
- VLSI
- Integrated Circuit Design
- RTL design
- Circuit Design
- Microprocessors
- SoC
- Logic Design
- Cadence Virtuoso
- EDA
- Perl
- CMOS
- Computer Architecture
- Synopsys tools
- ARM
- RTL coding
- IC
- Hardware Architecture
- Debugging
- Application-Specific Integrated Circuits (ASIC)
- DFT
- Application Specific Integrated Circuits Asic
- Design
- Application Specific Integrated Circuits
Tejas Raval Summary
- Tejas Raval, based in Santa Clara, CA, US, is currently a Physical Design Engineer at Intel Corporation. Tejas Raval brings experience from previous roles at Qualcomm, Electrical Engineering Department, California State University, Northridge and INMED Equipments Pvt. Ltd. Tejas Raval holds a 2010 - 2012 MS Electrical in ASIC/FPGA Design @ California State University-Northridge. With a robust skill set that includes Verilog, ASIC, Matlab, TCL, Static Timing Analysis and more. Tejas Raval has 4 emails and 2 mobile phone numbers on RocketReach.
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