Te-Chen Tsai Email & Phone Number
Member of Technical Staff @ Density AI
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Te-Chen Tsai Location
- Santa Clara, CA, US
Te-Chen Tsai Work
- Member of Technical Staff @ (November 2025 - Present)
- Autopilot hardware engineer @ (May 2018 - October 2025)
- Physical Design Engineer @ Intel Corporation (October 2016 - April 2018)
- Physical Design Engineer @ (June 2013 - September 2016)
- Senior Design Engineer @ (May 2010 - May 2013)
- Design Engineer 2 @ (February 2007 - April 2010)
- Intern @ (May 2006 - August 2006)
Te-Chen Tsai Education
- Carnegie Mellon University
Master (Electrical and Computer Engineering)
2005-2007 - National Chiao Tung University
Bachelor (Electonics Engineering)
1999-2003
Te-Chen Tsai Skills
- ASIC
- Circuit Design
- Computer Architecture
- Integrated Circuit Design
- Logic Design
- Physical Design
- SoC
- Static Timing Analysis
- Timing Closure
- VLSI
- Verilog
Te-Chen Tsai Summary
- Te-Chen Tsai, based in Santa Clara, CA, US, is currently a Member of Technical Staff at DensityAI. Te-Chen Tsai brings experience from previous roles at Tesla, Intel Corporation, Soft Machines and AMD. Te-Chen Tsai holds a 2005 - 2007 Master in Electrical and Computer Engineering @ Carnegie Mellon University. With a robust skill set that includes ASIC, Circuit Design, Computer Architecture, Integrated Circuit Design, Logic Design and more. Te-Chen Tsai has 2 emails and 2 mobile phone numbers on RocketReach.
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