Tanuj Jindal's Location
Bengaluru, KA, IN
Tanuj Jindal's Work
- SoC Physical Design and Timing Lead Engineer @ Intel Corporation
- Physical Design and Timing Engineer @ Intel Corporation
- Senior Staff Engineer @ Broadcom
- Staff II- IC Design @ Broadcom
- Component Design Engineer @ Intel Corporation
- Intern @ AMD
- Design Engineer @ Texas Instruments
Tanuj Jindal's Education
- Texas A&M University
M.S. (Electrical & Computer Engineering)
2008 - 2010 - Indian Institute of Technology, Roorkee
B.Tech (Electrical Engineering)
2002 - 2006
Tanuj Jindal's Skills
- Static Timing Analysis
- Perl
- VLSI
- Primetime
- Debugging
- Simulations
- Verilog
- EDA
- Algorithms
- Hardware Architecture
Tanuj Jindal's Summary
Tanuj Jindal, based in Bengaluru, KA, IN, is currently a SoC Physical Design and Timing Lead Engineer at Intel Corporation, bringing experience from previous roles at Intel Corporation and Broadcom. Tanuj Jindal holds a 2008 - 2010 M.S. in Electrical & Computer Engineering @ Texas A&M University. With a robust skill set that includes Static Timing Analysis, Perl, VLSI, Primetime, Debugging and more, Tanuj Jindal contributes valuable insights to the industry. Tanuj Jindal has 4 emails on RocketReach.
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