Tal Yahav Email & Phone Number
Senior Hardware Design Verification Engineer @ Apple
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Tal Yahav Location
- Palo Alto, CA, US
Tal Yahav Work
- Senior Hardware Design Verification Engineer @ (March 2024 - Present)
- Sr Staff @ (January 2016 - March 2024)
- Staff Verification eng @ (May 2012 - March 2024)
- Teaching Assistant @ (October 2009 - March 2024)
- Sr. Verification Eng @ (October 2010 - May 2012)
- VLSI Verification Eng. @ CVS - Chip Solutions (May 2009 - October 2010)
- Chip Design Eng @ (May 2006 - January 2009)
Tal Yahav Education
- Technion - Israel Institute of Technology
BS Electrical Engineering (Micro-electronics, control systems)
2002-2006 - Technion - Israel Institute of Technology
Engineer’s Degree (Electrical and Electronics Engineering)
2002-2005
Tal Yahav Skills
- AMBA AHB
- ASIC
- C
- Debugging
- Embedded Systems
- FPGA
- Formal Verification
- Functional Verification
- Logic Design
- Microprocessors
- PCIe
- Perl
- RTL Design
- Semiconductors
- SoC
- Specman
- SystemVerilog
- UFS
- UPF
- UVM
- VLSI
- VLSI CAD
- Verilog
- Very-Large-Scale Integration (VLSI)
- gatelevel verification
- power aware verification
- powere aware verification
Tal Yahav Summary
- Tal Yahav, based in Palo Alto, CA, US, is currently a Senior Hardware Design Verification Engineer at Apple. Tal Yahav brings experience from previous roles at Qualcomm, Technion - Israel Institute of Technology and CSR. Tal Yahav holds a 2002 - 2006 BS Electrical Engineering in Micro-electronics, control systems @ Technion - Israel Institute of Technology. With a robust skill set that includes AMBA AHB, ASIC, C, Debugging, Embedded Systems and more. Tal Yahav has 1 emails and 1 mobile phone numbers on RocketReach.
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