Tae-Sun Lim Email & Phone Number
SoC and Layout Design Engineer @ Intel Corporation
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Tae-Sun Lim Location
- Portland, OR, US
Tae-Sun Lim Work
- 2019 -now SoC and Layout Design Engineer @
- 2011 -2019 Lithography Process Development Engineer @
- 2007 -2011 Ph.D. in Electrical Engineering @
Tae-Sun Lim Education
- UC Irvine
Ph.D. (Electrical Engineering)
2007-2011 - Yonsei University 1997-2004
Tae-Sun Lim Skills
- Microfluidics
- BioMEMS
- Microfabrication
- MEMS
- Biosensors
- Nanofabrication
- Nanotechnology
- Semiconductor Device
- Thin Films
- Photolithography
- Design of Experiments
- Device Characterization
- Carbon Nanotubes
- AFM
- Biochemistry
- Biomedical Engineering
- CMOS
- COMSOL
- CVD
- Characterization
- Clean Rooms
- EDX
- Electrical Engineering
- Electron Beam Lithography
- Ellipsometry
- Etching
- FIB
- Failure Analysis
- IC
- Lithography
- Materials Science
- Microelectronics
- Nanomaterials
- JMP
- Labview
- Matlab
- Optics
- PECVD
- PVD
- Photonics
- Physics
- Plasma Physics
- Polymers
- Powder X-ray Diffraction
- R&D
- Semiconductors
- Sensors
- TEM
- Sputtering
- Semiconductor Process
- Development
- Technology
- Powder X Ray Diffraction
- Product Development
- Technology Development
Tae-Sun Lim Summary
- Tae-Sun Lim, based in Portland, OR, US, is currently a SoC and Layout Design Engineer at Intel Corporation. Tae-Sun Lim brings experience from previous roles at Intel Corporation and UC Irvine. Tae-Sun Lim holds a 2007 - 2011 Ph.D. in Electrical Engineering @ UC Irvine. With a robust skill set that includes Microfluidics, BioMEMS, Microfabrication, MEMS, Biosensors and more. Tae-Sun Lim has 4 emails and 1 mobile phone numbers on RocketReach.
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