Syed Kaiser Email & Phone Number
Patent Examiner @ USPTO
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Syed Kaiser Location
- Belle Haven, VA, US
Syed Kaiser Work
- 2013 -now Patent Examiner @
- 2013 -2013 Analog and Mixed-Signal IC Design Consultant @
- 2011 -2012 Video Analog Designer @
- 2000 -2009 Senior Analog Designer @
- 1999 -2000 Graduate Teaching Assisstant @ UNIVERSITY OF TEXAS
Syed Kaiser Education
- University of Texas at Arlington (UTA)
M.S (Electrical engineering; VLSI design)
1998-2000 - Bangladesh University of Engineering and Technology
B.S (Electrical engineering; Electronics)
1989-1993
Syed Kaiser Skills
- Cadence Virtuoso
- Analog Circuit Design
- Debugging
- Physical Verification
- SPICE
- Analog
- Spectre
- ASIC
- VLSI
- Verilog
- Integrated Circuit Design
- Circuit Design
- CMOS
- SoC
- EDA
- Analog Design
- Semiconductors
- Cadence Spectre
- Simulations
- Static Timing Analysis
- Low Power Design
- Silicon
- IC
Syed Kaiser Summary
- Syed Kaiser, based in Belle Haven, VA, US, is currently a Patent Examiner at USPTO. Syed Kaiser brings experience from previous roles at AMD, Texas Instruments, FREESCALE SEMICONDUCTOR, INC and UNIVERSITY OF TEXAS. Syed Kaiser holds a 1998 - 2000 M.S in Electrical engineering; VLSI design @ University of Texas at Arlington (UTA). With a robust skill set that includes Cadence Virtuoso, Analog Circuit Design, Debugging, Physical Verification, SPICE and more. Syed Kaiser has 3 emails and 3 mobile phone numbers on RocketReach.
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