Suraj Avinash Email & Phone Number
TPU Hardware Engineer, Technology and DTCO @ Google
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Suraj Avinash Location
- San Jose, CA, US
Suraj Avinash Work
- TPU Hardware Engineer, Technology and DTCO @ (August 2026 - Present)
- Hardware Engineer, Technology and PPA @ (July 2022 - July 2026)
- Physical Design Engineer, DDR @ (June 2019 - June 2022)
- Senior Application Engineer @ (July 2015 - July 2017)
- Physical Design Engineer @ (June 2011 - February 2015)
Suraj Avinash Education
- Portland State University
Masters in Electrical and Computer Engineering (Computer Architecture and Design)
2017-2019 - Visvesvaraya Technological University
Bachelor of Engineering (B.E.) (Electronics and Communications Engineering)
2007-2011
Suraj Avinash Skills
- Physical Design
- Static Timing Analysis
- TCL
- VLSI
- Perl
- ASIC
- SoC
- Integrated Circuit Design
- LVS
- Timing Closure
- Debugging
- Logic Synthesis
- Timing
- Physical Verification
- Processors
- PhpMyAdmin
- jQuery
- HTML5
- ASP.NET
- Ic Design
- Design
- Very Large Scale Integration Vlsi
- IC
- Very Large Scale Integration
Suraj Avinash Summary
- Suraj Avinash, based in San Jose, CA, US, is currently a TPU Hardware Engineer, Technology and DTCO at Google. Suraj Avinash brings experience from previous roles at Microsoft, Qualcomm, Ausdia Inc. and Broadcom Limited. Suraj Avinash holds a 2017 - 2019 Masters in Electrical and Computer Engineering in Computer Architecture and Design @ Portland State University. With a robust skill set that includes Physical Design, Static Timing Analysis, TCL, VLSI, Perl and more. Suraj Avinash has 2 emails and 1 mobile phone numbers on RocketReach.
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