Sudhanshu Saxena's Location
Bengaluru, KA, IN
Sudhanshu Saxena's Work
- Engineering Manager [Verification and Validation] @ Intel Corporation
- Expert Engineer FPGA and ASIC Validation @ Infineon Technologies
- Senior Engineer, SoC Product Validation @ Microsemi Corporation
- FPGA Consultant @ Computational Research Laboratories Limited (Pune)
- Module Leader [ASIC and FPGA Design] @ Wipro
- FPGA Design enginner @ Sasken Communication
Sudhanshu Saxena's Education
- Nirma University, Ahmedabad, Gujarat, India
Master of Technology - MTech (VLSI Design)
2003 - 2005 - Bhilai Institute of Technology (BIT), Durg
Bachelor of Engineering - BE (Electrical and Electronics Engineering)
Sudhanshu Saxena's Skills
- Timing Closure
- Logic Synthesis
- VLSI
- Xilinx
- Timing
- NCSim
- Clock Tree Synthesis
- RTL coding
- Static Timing Analysis
- SystemVerilog
Sudhanshu Saxena's Summary
Sudhanshu Saxena, based in Bengaluru, KA, IN, is currently a Engineering Manager [Verification and Validation] at Intel Corporation, bringing experience from previous roles at Infineon Technologies, Microsemi Corporation, Computational Research Laboratories and Wipro Technologies. Sudhanshu Saxena holds a 2003 - 2005 Master of Technology - MTech in VLSI Design @ Nirma University, Ahmedabad, Gujarat, India. With a robust skill set that includes Timing Closure, Logic Synthesis, VLSI, Xilinx, Timing and more, Sudhanshu Saxena contributes valuable insights to the industry. Sudhanshu Saxena has 2 emails on RocketReach.
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