Sudeshna Mitra Email & Phone Number
Silicon Design Engineer @ AMD
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Sudeshna Mitra Location
- San Jose, CA, US
Sudeshna Mitra Work
- Silicon Design Engineer @ (November 2022 - Present)
- ASIC integration Engineer @ (March 2022 - November 2022)
- Principal Engineer @ (April 2017 - March 2022)
- Staff Engineer @ (March 2016 - March 2017)
- Synthesis and STA Consultant @ (February 2015 - March 2016)
- Staff Digital Design Engineer @ (December 1997 - November 2014)
Sudeshna Mitra Education
- San Jose State University 1996-1997
Sudeshna Mitra Skills
- Conformal Lec
- C/C++
- Perl Script
- Logic Synthesis
- DFT
- ASIC
- Verilog
- TCL
- Formality
- Power Theater
- Ptsi
- Dft Fastscan
- SoC
- VHDL
- VCS
- ModelSim
- Primetime Pt
- Fishtail
- Timing Closure
- Dft Compiler
- Static Timing Analysis
- Design Compiler Dc and Dct
- Pt Dmsa
- Verdi
- IC
- Primetime
- Design Compiler
Sudeshna Mitra Summary
- Sudeshna Mitra, based in San Jose, CA, US, is currently a Silicon Design Engineer at AMD. Sudeshna Mitra brings experience from previous roles at Intel Corporation, Western Digital, SanDisk and Infinera Corporation. Sudeshna Mitra holds a 1996 - 1997 San Jose State University. With a robust skill set that includes Conformal Lec, C/C++, Perl Script, Logic Synthesis, DFT and more. Sudeshna Mitra has 2 emails and 2 mobile phone numbers on RocketReach.
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