MESI Protocol for Cacche Coherency in Multicore Architecture.
Mixed Signal
Mixed Signal Verification
Object-Oriented Programming (OOP)
Perl
Phase-Locked Loop (PLL)
Silicon Bringup
SoC
System Verilog
SystemVerilog
USB PHY
UVM
VMM
Verification Methodologies: VMM & UVM
Verilog
Vmm and Uvm
Design
Hvl
Ic Design
Verification Methodologies
Mesi Protocol for Cacche Coherency in Multicore Architecture
Platform
IC
Clock Domain Crossing
Phase Locked Loop
Subham Banerjee Summary
Subham Banerjee, based in Cork, IE, is currently a Principal Design Verification Architect and EMEA IP Lead at AMD. Subham Banerjee brings experience from previous roles at Qualcomm, Intel Corporation and Xilinx. Subham Banerjee holds a 2002 - 2006 B.Tech in Electronics @ Kalyani Govt. Engineering College(K.G.E.C). With a robust skill set that includes ASIC, AXI-Lite & APB3, C++, C/C++, Clock Domain Crossing and more. Subham Banerjee has 2 emails on RocketReach.
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