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Stéphane Guez Location
Paris, FR
Stéphane Guez Work
Director of Engineering @ (March 2023 - Present)
High Performance Computing ASIC and FPGA Logic Design R and D Manager @ (February 2021 - December 2023)
5G BaseBand FPGA and SoC Line Manager @ (April 2017 - February 2021)
Senior Component Engineer @ (April 2010 - March 2017)
Technical Project Leader @ (June 2008 - March 2010)
Senior Design Leader @ (February 2002 - May 2008)
Junior Design leader @ (April 2001 - January 2002)
LORE Senior Consultant acting as SoC Architect @ (May 1999 - March 2001)
SOREP Consultant acting as digital ASIC designer @ (August 1997 - April 1999)
Digital ASIC design responsible @ (March 1996 - July 1997)
Digital ASIC Designer @ (April 1995 - February 1996)
ASIC Junior Designer @ (January 1994 - March 1995)
Stéphane Guez Education
Jussieu (Paris Vii University) 1989-1993
Université Pierre et Marie Curie (Paris VI)
Masters
1992-1992
Stéphane Guez Skills
ARM
ASIC
Active and Passive components technology
Analog
Application-Specific Integrated Circuits (ASIC)
CMOS
Components
Components failure mechanisms
DFT
Design For Testability techniques
Digital Signal Processors
EDA
Electronics
Embedded Systems
Excel Visual Basic development expert
Experience with EDA tools such as Design Compiler, Physical Compiler
IC
Low-power Design
Mobile Devices
Modeling Languages: VHDL and Verilog
Project Management
Semiconductors
SoC
Strong transistor level design experience
System on a Chip (SoC)
VHDL
Verilog
Wafer dicing, dies inspection, storage and procurement
Technology
Social Media
Storage And Procurement
System On A Chip Soc
Wafer Dicing
Strategic Planning
Physical Compiler
Modeling Languages
Marketing
Application Specific Integrated Circuits Asic
Manufacturing
Vhdl And Verilog
Die
Design
Baseband
Experience With Eda Tools Such As Design Compiler
Management
Software Development
Low Power Design
Architecture
Integration
Dies Inspection
Application Specific Integrated Circuits
System on a Chip
Stéphane Guez Summary
Stéphane Guez, based in Paris, FR, is currently a Director of Engineering at SCALINX. Stéphane Guez brings experience from previous roles at Atos, Nokia, Schlumberger and ST-Ericsson. Stéphane Guez holds a 1989 - 1993 Jussieu (Paris Vii University). With a robust skill set that includes ARM, ASIC, Active and Passive components technology, Analog, Application-Specific Integrated Circuits (ASIC) and more. Stéphane Guez has 1 emails on RocketReach.
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