PROFESSIONAL TRAINING (SYSTEM VERILOG FOR ADVANCED DESIGN VERIFICATION)
2011 - 2011
San Jose State University
Masters (VLSI- ASIC / FPGA DESIGN AND VERIFICATION)
2009 - 2011
AITS
BS (ELECTRONICS AND COMMUNICATIONS ENGINEERING)
2004 - 2008
Sri Panchanam's Skills
SystemVerilog
Design
UVM
Embedded Systems
ASIC
Debugging
VMM
FPGA
SoC
Verilog
Sri Panchanam's Summary
Sri Panchanam, based in San Jose, CA, US, is currently a staff design verification engineer at XPENG, bringing experience from previous roles at Cisco, Marvell Semiconductor and Intel Corporation. Sri Panchanam holds a 2011 - 2011 PROFESSIONAL TRAINING in SYSTEM VERILOG BASICS @ IEEE BOSTON. With a robust skill set that includes SystemVerilog, Design, UVM, Embedded Systems, ASIC and more, Sri Panchanam contributes valuable insights to the industry. Sri Panchanam has 3 emails and 1 mobile phone number on RocketReach.