Siew Yeoh Email
VP of Engineering @ Lattice Semiconductor
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Siew Yeoh Location
- Bayan Lepas, MY
Siew Yeoh Work
- 2024 -now VP of Engineering @
- 2022 -now Senior Director, Systems and IP Engineering @
- 2019 -2022 Director Of Design Engineering @
- 2015 -2019 Director, Test Engineering @
- 2008 -2015 Senior Design Manager @ Altera
- 2001 -2008 Section Head, Test Development @ Altera
Siew Yeoh Education
- RMIT University
Bachelor’s Degree of Engineering (Computer System Engineering)
1997-2000
Siew Yeoh Skills
- IC
- ASIC
- FPGA
- RTL design
- SoC
- Semiconductors
- VLSI
- Product Development
- Project Management
- Process Improvement
- Cross-functional Team Leadership
- DFT
- Design
- Test Engineering
- Cross Functional Team Leadership
- Altera
Siew Yeoh Summary
- Siew Yeoh, based in Bayan Lepas, MY, is currently a VP of Engineering at Lattice Semiconductor. Siew Yeoh brings experience from previous roles at Lattice Semiconductor, Intel Corporation and Altera. Siew Yeoh holds a 1997 - 2000 Bachelor’s Degree of Engineering in Computer System Engineering @ RMIT University. With a robust skill set that includes IC, ASIC, FPGA, RTL design, SoC and more. Siew Yeoh has 2 emails on RocketReach.
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