Sidharth Iyer Email
Analog Validation Engineer @ Texas Instruments
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Sidharth Iyer Location
- Kottayam, KL, IN
Sidharth Iyer Work
- Analog Validation Engineer @ (July 2024 - Present)
- Analog Validation Intern @ (January 2024 - June 2024)
- Analog Engineering Intern @ (May 2023 - July 2023)
- Hardware Intern @ (May 2022 - June 2022)
- Head of Lecture Committee @ (May 2022 - October 2022)
- Joint Secretary @ (January 2022 - February 2023)
- Member @ (October 2021 - July 2023)
Sidharth Iyer Education
- National Institute of Technology Calicut
Bachelor of Technology - BTech (Electrical and Electronics Engineering)
2020-2024
Sidharth Iyer Summary
- Sidharth Iyer, based in Kottayam, KL, IN, is currently a Analog Validation Engineer at Texas Instruments. Sidharth Iyer brings experience from previous roles at Texas Instruments, Defence Research and Development Laboratory (DRDL) - DRDO and Tathva NIT Calicut. Sidharth Iyer holds a 2020 - 2024 Bachelor of Technology - BTech in Electrical and Electronics Engineering @ National Institute of Technology Calicut. Sidharth Iyer has 2 emails on RocketReach.
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