Sheetal S Email
Design verification engineer @ Capgemini Engineering
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Sheetal S Location
- Bengaluru, KA, IN
Sheetal S Work
- 2022 -now Design verification engineer @
- 2019 -2022 Design Verification Engineer @
- 2017 -2019 Design Verification Engineer @
- 2016 -2017 Design Engineer @ Asarva Chips & Technologies Pvt Ltd
- 2016 -2016 Intern @ Asarva Chips & Technologies Pvt Ltd
Sheetal S Education
- PES University
Master of Technology (M.Tech.) (VLSI & ES)
2013-2015 - SRSIT
Bachelor of Engineering (B.E.) (Electronics and Communications Engineering)
2009-2013 - Vijaya pre university college 2007-2009
Sheetal S Summary
- Sheetal S, based in Bengaluru, KA, IN, is currently a Design verification engineer at Capgemini Engineering. Sheetal S brings experience from previous roles at Altran, Aricent and Asarva Chips & Technologies Pvt Ltd. Sheetal S holds a 2013 - 2015 Master of Technology (M.Tech.) in VLSI & ES @ PES University. Sheetal S has 1 emails on RocketReach.
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