Sheetal Jain Email & Phone Number
Semiconductor Packaging Architect, Co-design and SI and PI Lead @ cspeed inc
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Sheetal Jain Location
- Bengaluru, KA, IN
Sheetal Jain Work
- Semiconductor Packaging Architect, Co-design and SI and PI Lead @ (March 2026 - Present)
- IC Package Architect and Platform Co-Design @ Ola Krutrim AI (January 2025 - March 2026)
- Package System Architect @ (November 2014 - May 2025)
- Design Manager @ (May 2011 - November 2014)
- Staff Engineer @ (January 2008 - May 2011)
- Manager, Product Engineering @ (April 2006 - January 2008)
- Team and Tech Lead, Mixed Signal CAD group @ (August 2004 - April 2006)
- SMTS @ (December 1999 - July 2004)
- Scientist and Engr C @ (January 1997 - January 1999)
Sheetal Jain Education
- Indian Institute of Technology, Delhi
Master's Degree (VDTT)
2001-2004 - jabalpur engineering college
Bachelor's Degree (Electronics & Telecom Engg)
1992-1996
Sheetal Jain Skills
- SoC
- Physical Design
- Mixed Signal
- ASIC
- IC
- Semiconductors
- CMOS
- VLSI
- Integrated Circuit Design
- Analog
- Analog Circuit Design
- EDA
- Static Timing Analysis
- Cadence
- Timing Closure
- Debugging
- Design
- Intel
- Engineering
- System on a Chip
- Very Large Scale Integration
- Application Specific Integrated Circuits
Sheetal Jain Summary
- Sheetal Jain, based in Bengaluru, KA, IN, is currently a Semiconductor Packaging Architect, Co-design and SI and PI Lead at cspeed inc. Sheetal Jain brings experience from previous roles at Ola Krutrim AI, Intel Corporation, Ericsson and Infineon Technologies India Pvt Ltd. Sheetal Jain holds a 2001 - 2004 Master's Degree in VDTT @ Indian Institute of Technology, Delhi. With a robust skill set that includes SoC, Physical Design, Mixed Signal, ASIC, IC and more. Sheetal Jain has 2 emails and 1 mobile phone numbers on RocketReach.
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Top cspeed inc Employees
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Los Altos, CA, US
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California, United States
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San Diego, CA, US
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Palo Alto, CA, US
Arnab Goswami
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Chennai, TN, IN
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Mountain View, CA, US
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San Francisco, CA, US
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