Shao Wang Email & Phone Number
Sr. ASIC Design Manager @ Qorvo, Inc.
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Shao Wang Location
- San Jose, CA, US
Shao Wang Work
- Sr. ASIC Design Manager @ (April 2021 - Present)
- Design Director @ (September 2017 - April 2021)
- Technical Committee Member @ IEEE International Conference on ASIC 2019 (March 2019 - October 2019)
- Technical Committee Member and Session Chair @ IEEE International Conference on ASIC 2017 (March 2017 - October 2017)
- PMTS @ (July 1999 - August 2017)
- Design Engineer @ (May 1994 - July 1999)
- Research Assistant @ Cockrell School of Engineering, The University of Texas at Austin (January 1991 - June 1991)
Shao Wang Education
- Cockrell School of Engineering, The University of Texas at Austin
Doctor of Philosophy - PhD (Department of Electrical and Computer Engineering)
1991-1998
Shao Wang Skills
- Application-Specific Integrated Circuits (ASIC)
- Circuit Design
- DFT
- Electronics
- Floor Plans
- Global Distribution Systems (GDS)
- Integrated Circuits (IC)
- Layout Versus Schematic (LVS)
- Logic Design
- Logic Gates
- Microarchitecture
- Mixed Signal
- Semiconductor Industry
- Semiconductors
- Silicon Validation
- System on a Chip (SoC)
- Tape
- Verilog
Shao Wang Summary
- Shao Wang, based in San Jose, CA, US, is currently a Sr. ASIC Design Manager at Qorvo, Inc.. Shao Wang brings experience from previous roles at NextInput, IEEE International Conference on ASIC 2019, IEEE International Conference on ASIC 2017 and Maxim Integrated. Shao Wang holds a 1991 - 1998 Doctor of Philosophy - PhD in Department of Electrical and Computer Engineering @ Cockrell School of Engineering, The University of Texas at Austin. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), Circuit Design, DFT, Electronics, Floor Plans and more. Shao Wang has 1 emails on RocketReach.
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