ASIC and FPGA Front-End Engineer – Design and Verification (Professional Practical Program) @ Chip Design College
FPGA Design and HW Engineer @ CES (Computerized Electricity Systems)
Sergey Dubinin's Education
Cadence
UVM/SystemVerilog | Austria
2014 - 2014
Cadence
SystemVerilog for Design | Austria
2016 - 2016
Cadence
Formal verification with SVA (SystemVerilog Assertions) | Germany
2015 - 2015
Chip Design College, Ramat-Gan
ASIC/FPGA Front-End Engineer Professional Program (VLSI (Semiconductors) | Israel)
2009 - 2010
Satris Group Ltd.
Verification Course (SystemVerilog for Verification | Israel)
2012 - 2012
Austrian Testing Board
ISTQB Certified Tester | Austria
2016 - 2016
Braude Academic College
Bachelor Degree (Electronics Engineering)
2002 - 2006
AMAL High School, Nahariya
Practical Engineer (Electronics)
2000 - 2002
Sergey Dubinin's Skills
Hardware Architecture
Logic Design
RF
Linux
Field Programmable Gate Arrays Fpga
Debugging
System on a Chip Soc
System Verilog
Logic Synthesis
Perl
Sergey Dubinin's Summary
Sergey Dubinin, based in Styria, Austria, is currently a Staff Digital Design and Functional Verification Engineer | Connected Secure Systems dpt. at Infineon Technologies, bringing experience from previous roles at Infineon Technologies, NXP Semiconductors, Opgal and Elisra. Sergey Dubinin holds a 2014 - 2014 UVM/SystemVerilog | Austria @ Cadence. With a robust skill set that includes Hardware Architecture, Logic Design, RF, Linux, Field Programmable Gate Arrays Fpga and more, Sergey Dubinin contributes valuable insights to the industry. Sergey Dubinin has 3 emails and 1 mobile phone number on RocketReach.