Seice Kao's Location
London, GB
Seice Kao's Work
- Senior Digital Design Engineer @ 奇景光電股份有限公司
- Digital Design Engineer @ Silicon Integrated System Crop.
- Television RD Engineer @ Tatung Company
Seice Kao's Education
- University of Westminster
Master of Science (System-On-Chip Design for DSP and Communications)
2007 - 2009
Seice Kao's Skills
- FPGA
- SoC
- ModelSim
- Simulink
- Static Timing Analysis
- Verilog
- Matlab
- Pspice
- Testing
- RTL coding
Seice Kao's Summary
Seice Kao, based in London, GB, is currently a Senior Digital Design Engineer at Himax, bringing experience from previous roles at Silicon Integrated System Crop. and Tatung Company. Seice Kao holds a 2007 - 2009 Master of Science in System-On-Chip Design for DSP and Communications @ University of Westminster. With a robust skill set that includes FPGA, SoC, ModelSim, Simulink, Static Timing Analysis and more, Seice Kao contributes valuable insights to the industry. Seice Kao has 2 emails on RocketReach.
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