Satyanarayana Arvapalli's Location

Santa Clara, CA, US

Satyanarayana Arvapalli's Work

  • Tech Lead Manager - Design Verification @ Meta
  • Asic and Fpga Engineer @ Meta
  • Member of Technical Staff @ Innovium Inc.

Satyanarayana Arvapalli's Education

  • Indian Institute of Technology

    Master Of Technology

    2001 - 2003
  • College Of Engineering, Osmania

    Bachelors (Electronics Engineering)

Satyanarayana Arvapalli's Skills

  • ASIC
  • Functional Verification
  • Verilog
  • SystemVerilog
  • SoC
  • Debugging
  • IC
  • C
  • VLSI
  • FPGA

Satyanarayana Arvapalli's Summary

Satyanarayana Arvapalli, based in Santa Clara, CA, US, is currently a Tech Lead Manager - Design Verification at Facebook, bringing experience from previous roles at Facebook, Innovium Inc., Qualcomm Cambridge and Brocade. Satyanarayana Arvapalli holds a 2001 - 2003 Master Of Technology @ Indian Institute of Technology. With a robust skill set that includes ASIC, Functional Verification, Verilog, SystemVerilog, SoC and more, Satyanarayana Arvapalli contributes valuable insights to the industry. Satyanarayana Arvapalli has 3 emails and 1 mobile phone number on RocketReach.

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