2011 -2011 Lead Consultant. @ Infosys Technologies Limited.
2008 -2011 Lead Design Engineer @
2001 -2008 Lead Design Engineer @ Texas Instruments India Pvt Ltd
1999 -2001 Lead Design Engineer @
1996 -1998 Engr (Branch head Pune) @
Sanjay Shinde Education
ACTS CDAC Pune
PG Diploma VLSI
1998-1998
Savitribai Phule Pune University
BE E&TC
1992-1996
Cusrow Wadia Institute of Technology Pune
DERE
1989-1991
H A School Pimpri. 1984-1987
Sanjay Shinde Skills
Timing Closure
SoC
RTL design
Semiconductors
Static Timing Analysis
Primetime
ASIC
IC
Logic Synthesis
Functional Verification
Physical Design
VLSI
DFT
Formal Verification
Verilog
EDA
SystemVerilog
TCL
Low-power Design
Microarchitecture
RTL coding
FPGA
NCSim
Integrated Circuit Design
AMBA AHB
Debugging
System on a Chip (SoC)
Very-Large-Scale Integration (VLSI)
Application-Specific Integrated Circuits (ASIC)
Power
Field Programmable Gate Arrays Fpga
System on a Chip Soc
Integrated Circuits Ic
Application Specific Integrated Circuits Asic
Design
Low Power Design
Very Large Scale Integration Vlsi
Services
System on a Chip
Very Large Scale Integration
Application Specific Integrated Circuits
Integrated Circuits
Field Programmable Gate Arrays
Sanjay Shinde Summary
Sanjay Shinde, based in Bengaluru, KA, IN, is currently a Director Silicon Design Engineering. at AMD. Sanjay Shinde brings experience from previous roles at Intel Corporation, Micron Technology, Cientra (Formerly Mindlance Technologies) and Mindlance Technologies. Sanjay Shinde holds a 1998 - 1998 PG Diploma VLSI @ ACTS CDAC Pune. With a robust skill set that includes Timing Closure, SoC, RTL design, Semiconductors, Static Timing Analysis and more. Sanjay Shinde has 3 emails and 3 mobile phone numbers on RocketReach.
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