Senior Validation Engineer @ (March 2021 - October 2023)
Senior Design Verification Engineer @ (March 2016 - March 2021)
Design Verification Engineer @ (June 2012 - March 2016)
HEP trainee @ (May 2011 - July 2011)
Sandhya Garg Education
MDU ,rohtak
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
2007-2011
Apeejay School,Faridabad 2004-2006
Sandhya Garg Summary
Sandhya Garg, based in Bengaluru, KA, IN, is currently a Manager Silicon Design Engineering at AMD. Sandhya Garg brings experience from previous roles at Google, Intel Corporation, Qualcomm and Orange Research Labs. Sandhya Garg holds a 2007 - 2011 Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering @ MDU ,rohtak. Sandhya Garg has 3 emails and 1 mobile phone numbers on RocketReach.
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