Saikumar Megavath Email & Phone Number
Senior Design Verification Engineer @ AIonSi
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Saikumar Megavath Location
- Bengaluru, KA, IN
Saikumar Megavath Work
- Senior Design Verification Engineer @ (August 2025 - Present)
- Senior Verification Engineer @ (July 2024 - May 2025)
- Lead Engineer DV @ (December 2022 - June 2024)
- Design Verification Engineer @ (March 2020 - November 2022)
- Junior Engineer @ (January 2018 - February 2020)
- VLSI Trainee @ Jagruti Technosys Pvt Ltd (June 2017 - December 2017)
Saikumar Megavath Education
- BV Raju Institute of Technology (BVRIT)
Bachelor of Technology - BTech (Electrical, Electronics and Communications Engineering)
2014-2017 - Teegala Ram Reddy College of Polytechnic
Diploma in engineering (Electronics and Communications Engineering)
2014 - PVHS
SSC
2010
Saikumar Megavath Skills
- Verilog
- system verilog
- Universal Verification Methodology (UVM)
- Microcontrollers
- Field-Programmable Gate Arrays (FPGA)
- Perl
- Microsoft Office
- C
- Linux
- Xilinx Vivado
- QuestaSim
- Verdi
- Xilinx ISE
- ModelSim
- AMBA AHB
- SPI
- GLS
- vcs
- RTL Coding
- Application-Specific Integrated Circuits (ASIC)
- Functional Verification
- Debugging
- RTL Design
- Serial Protocols
- Assertions
- Engineering
Saikumar Megavath Summary
- Saikumar Megavath, based in Bengaluru, KA, IN, is currently a Senior Design Verification Engineer at AIonSi. Saikumar Megavath brings experience from previous roles at Interex semiconductor, Quest Global, BITSILICA and Altran. Saikumar Megavath holds a 2014 - 2017 Bachelor of Technology - BTech in Electrical, Electronics and Communications Engineering @ BV Raju Institute of Technology (BVRIT). With a robust skill set that includes Verilog, system verilog, Universal Verification Methodology (UVM), Microcontrollers, Field-Programmable Gate Arrays (FPGA) and more. Saikumar Megavath has 1 emails and 1 mobile phone numbers on RocketReach.
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