Sai Garimella's Location
San Jose, CA, US
Sai Garimella's Work
- Sr Engineer @ Apple
- Sr. STA Engineer @ Samsung Semiconductor, Inc.
- Senior ASIC Engineer @ Cyient
- Intern @ TES Electronic Solutions GmbH
Sai Garimella's Education
- Technische Universität Darmstadt
Master of Science
2004 - 2007 - Jawaharlal Nehru Technological University
Bachelor of Technology (Communication, Engineering, Electronics)
2000 - 2004 - Siddhartha Public School
Sai Garimella's Skills
- VLSI
- Verilog
- ASIC
- Static Timing Analysis
- Timing Closure
- SoC
- DFT
- FPGA
- Logic Synthesis
- DDR
Sai Garimella's Summary
Sai Garimella, based in San Jose, CA, US, is currently a Sr Engineer at Apple Inc, bringing experience from previous roles at Samsung Semiconductor, Infotech Enterprises Electronic Design Services, Inc. and TES Electronic Solutions. Sai Garimella holds a 2004 - 2007 Master of Science @ Technische Universität Darmstadt. With a robust skill set that includes VLSI, Verilog, ASIC, Static Timing Analysis, Timing Closure and more, Sai Garimella contributes valuable insights to the industry. Sai Garimella has 2 emails on RocketReach.
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