Sai Akella Email & Phone Number
Senior IP Logic Design Engineer @ Intel Corporation
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Sai Akella Location
- California, United States
Sai Akella Work
- now
- 2024 -now Senior IP Logic Design Engineer @
- 2018 -2024 Senior SOC Design Engineer @
- 2015 -2018 Graphics Hardware Engineer @
- 2011 -2014 IC Design Engineer II @
- 2009 -2011 Graduate Research Assistant @
- 2010 -2010 Digital Design Intern @
- 2008 -2009 Graduate Teaching Assistant @
Sai Akella Education
- Villanova University
M.S (Electrical Engineering)
2008-2011 - Jawaharlal Nehru Technological University
Bachelors (Electronics and Communications)
2004-2008
Sai Akella Skills
- System Verilog
- Verilog
- RTL design
- ASIC Design
- Data Entry
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- VHDL
- Matlab
- Simulink
- Assembly Language
- Microsoft Office
- Microsoft Windows
- Red Hat Linux
- Perl
- Cadence
- Functional Verification
- Logic Synthesis
- Static Timing Analysis
- Synopsys Primetime
- Synopsys Design Compiler
- VCS
- Cadence Incisive
- Formality
- Spyglass
- Cadence Virtuoso Schematic Editor
- Cadence Simvision
- Verdi
- ENOVIA Synchronicity
- Altera Quartus
- ModelSim
- Synplify Pro
- Unix Operating Systems
- TCL
- SystemVerilog
- RTL Verification
Sai Akella Summary
- Sai Akella, based in California, United States, is currently a Senior IP Logic Design Engineer at Intel Corporation. Sai Akella brings experience from previous roles at AMD, Intel Corporation and LSI, an Avago Technologies Company. Sai Akella holds a 2008 - 2011 M.S in Electrical Engineering @ Villanova University. With a robust skill set that includes System Verilog, Verilog, RTL design, ASIC Design, Data Entry and more. Sai Akella has 4 emails and 2 mobile phone numbers on RocketReach.
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