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Ryan Munar Location
Hengelo, NL
Ryan Munar Work
2026 -now Lead Layout Engineer @
2018 -2026 Principal IC Layout Engineer @
2017 -2018 RF and Analog Layout Design Engineer @
2014 -2016 Senior IC Layout Design Engineer @
2010 -2013 Engineering Design Enablement @
2010 -2010 Design Automation and Physical Design Engineer @
2004 -2010 IC Layout Design Engineer @ Sanyo Manufacturing Corporation
Ryan Munar Education
Saint Louis University (PH)
Bachelor of Science (BS) (Electrical and Electronics Engineering)
1996-2003
Saint Louis University (PH)
Master's degree (Electrical and Electronics Engineering)
2009
Ryan Munar Skills
IC
DRC
Semiconductors
ASIC
LVS
CMOS
Physical Design
Virtuoso
Analog
Cadence
Layout Versus Schematic (LVS)
Design Rule Checking (DRC)
Cadence Virtuoso
EDA
Integrated Circuits (IC)
Application-Specific Integrated Circuits (ASIC)
Layout
Mixed Signal
RF
Signal Integrity
Floorplanning
SoC
Layout Versus Schematic Lvs
IVA
Design Rule Checking Drc
Integrated Circuits Ic
Application Specific Integrated Circuits Asic
IC layout
Design
Layout Versus Schematic
Design Rule Checking
Integrated Circuits
Application Specific Integrated Circuits
Ryan Munar Summary
Ryan Munar, based in Hengelo, NL, is currently a Lead Layout Engineer at Cyient Semiconductors. Ryan Munar brings experience from previous roles at Bruco Integrated Circuits B.V., NXP Semiconductors, Analog Devices and GLOBALFOUNDRIES Singapore PTE LTD. Ryan Munar holds a 1996 - 2003 Bachelor of Science (BS) in Electrical and Electronics Engineering @ Saint Louis University (PH). With a robust skill set that includes IC, DRC, Semiconductors, ASIC, LVS and more. Ryan Munar has 1 emails on RocketReach.
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