Rudresh Singh Email & Phone Number
Timing Lead @ Apple
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Rudresh Singh Location
- Austin, TX, US
Rudresh Singh Work
- 2015 -now Timing Lead @
- 2012 -now Sr. Physical Timing Engineer @
- 2009 -2012 Sr. ASIC Design Engineer @
- 2007 -2009 M.S. Computer Engineering @
- 2008 -2009 ASIC Intern @
- 2008 -2008 ASIC Intern @
- 2006 -2007 Design Engineer @
- 2005 -2006 ASIC Design Engineer @
Rudresh Singh Education
- Texas A&M University
M.S. (Computer Engineering)
2007-2008 - Indian Institute of Technology, Madras
B.Tech (Electronics)
2001-2005
Rudresh Singh Skills
- ASIC
- Static Timing Analysis
- Primetime
- VLSI
- Verilog
- Timing Closure
- Testing
- TCL
- Logic Synthesis
- SPICE
- Compilers
- Perl
- ARM
- Timing
- Physical Design
- Integrated Circuit Design
- Computer Architecture
- RTL design
- Simulations
- Project Management
- Management
- SoC
- Design
- PowerPoint
Rudresh Singh Summary
- Rudresh Singh, based in Austin, TX, US, is currently a Timing Lead at Apple. Rudresh Singh brings experience from previous roles at Apple, NVIDIA and Texas A&M University. Rudresh Singh holds a 2007 - 2008 M.S. in Computer Engineering @ Texas A&M University. With a robust skill set that includes ASIC, Static Timing Analysis, Primetime, VLSI, Verilog and more. Rudresh Singh has 3 emails and 1 mobile phone numbers on RocketReach.
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