Roy Geron Email
ASIC Design Manager @ Intel Corporation
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Roy Geron Location
- Israel
Roy Geron Work
- 2025 -now ASIC Design Manager @
- 2022 -2025 ASIC Design Team Leader and Chip Lead @
- 2022 -2022 ASIC Design Group Manager @
- 2019 -2022 Director of HW, VLSI and FPGA and Operation @
- 2016 -2019 VLSI and FPGA manager @
- 2014 -2016 Logic Design Engineer @
- 2009 -2014 Chip Design Leader @
- 2006 -2009 Chip Design Engineer at PMC-Sierra @
Roy Geron Education
- Ben Gurion University
first (Electrical & Computer Engineering)
2003-2007
Roy Geron Skills
- Hardware Architecture
- Logic Design
- Specman
- Debugging
- Functional Verification
- RTL design
- Microprocessors
- PCIe
- Processors
- ASIC
- Hardware Verification
- Verilog
- VLSI
- Team Leadership
- Embedded Systems
- RTL coding
- SoC
- Management
- Semiconductors
- Design
- Static Timing Analysis
- Microarchitecture
- Architecture
- R&D
- Hardware
- System Architecture
Roy Geron Summary
- Roy Geron, based in Israel, is currently a ASIC Design Manager at Intel. Roy Geron brings experience from previous roles at Google, NextSilicon and Lightbits Labs. Roy Geron holds a 2003 - 2007 first in Electrical & Computer Engineering @ Ben Gurion University. With a robust skill set that includes Hardware Architecture, Logic Design, Specman, Debugging, Functional Verification and more. Roy Geron has 2 emails on RocketReach.
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