Roy Geron Location
Israel
Roy Geron Work
- 2025 - now ASIC Design Manager @ Habana Labs
- 2022 - 2025 ASIC Design Team Leader and Chip Lead @ Google
- 2022 - 2022 ASIC Design Group Manager @ NextSilicon
- 2019 - 2022 Director of HW, VLSI and FPGA and Operation @ Lightbits Labs
- 2016 - 2019 VLSI and FPGA manager @ Lightbits Labs
- 2014 - 2016 Logic Design Engineer @ Apple
- 2009 - 2014 Chip Design Leader @ PMC-Sierra is now Microsemi
- 2006 - 2009 Chip Design Engineer at PMC-Sierra @ Wintegra
Roy Geron Education
- Ben Gurion University
first (Electrical & Computer Engineering)
2003 - 2007
Roy Geron Skills
- Hardware Architecture
- Logic Design
- Specman
- Debugging
- Functional Verification
- RTL design
- Microprocessors
- PCIe
- Processors
- ASIC
Roy Geron Summary
Roy Geron, based in Israel, is currently a ASIC Design Manager at Habana Labs. Roy Geron brings experience from previous roles at Google, NextSilicon and Lightbits Labs. Roy Geron holds a 2003 - 2007 first in Electrical & Computer Engineering @ Ben Gurion University. With a robust skill set that includes Hardware Architecture, Logic Design, Specman, Debugging, Functional Verification and more. Roy Geron has 2 emails on RocketReach.
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