Rotem Levy Email

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IPU Emulation and FPGA Team Manager @ (January 2024 - Present)
IPU Emulation Arch and U-Arch @ (January 2018 - January 2024)
Power Owner of the Smart-NIC ASIC @ (January 2016 - December 2018)
Arch, uArch and Tech-Lead for several Smart-NIC ASICs @ (January 2014 - December 2016)
Post-Silicon lead for ASIC product @ (January 2012 - December 2013)
uArch and Design-Lead of 10G-Lan-Controller ASICs @ (January 2005 - December 2011)
Design-Manager of the PHY-Logic team @ (January 2002 - December 2004)
H and W manager and Project Manager @ Trellis Photonics LTD (January 1999 - December 2002)
Senior ASIC Designer @ Ultracom Communication LTD (January 1998 - December 1999)
HW Team Leader @ Ornet / Siemens Data Communications (January 1996 - December 1998)
Asic design Team leader @ Ornet / Siemens Data Communications (January 1994 - December 1996)
ASIC Designer @ (January 1991 - December 1993)

Rotem Levy, based in Acre, IL, is currently a IPU Emulation and FPGA Team Manager at Intel Corporation. Rotem Levy brings experience from previous roles at Intel Corporation. Rotem Levy holds a 1989 - 1993 Technion - Israel Institute of Technology. With a robust skill set that includes Verilog, RTL design, VLSI, SoC, ASIC and more. Rotem Levy has 3 emails on RocketReach.