Rohan Parab Location
Sunnyvale, CA, US
Rohan Parab Work
- 2023 - now Sr. Design Verification Engineer @ AMD
- 2019 - 2023 Graphics Hardware Engineer @ Intel Corporation
- 2018 - 2019 Pre-si Validation Engineer @ UST
- 2017 - 2018 FPGA Prototyping Intern @ Synopsys Inc
- 2015 - 2016 Student Assistant - Academic Technology Computer Centre @ San Jose State University
Rohan Parab Education
- San Jose State University2014 - 2016
- University of Mumbai2009 - 2013
Rohan Parab Skills
- Cadence Virtuoso
- Linux
- Field Programmable Gate Arrays Fpga
- Debugging
- System On A Chip Soc
- Functional Verification
- Perl
- RTL design
- ASIC
- FPGA prototyping
Rohan Parab Summary
Rohan Parab, based in Sunnyvale, CA, US, is currently a Sr. Design Verification Engineer at AMD. Rohan Parab brings experience from previous roles at Intel Corporation, UST Global, Synopsys Inc and San Jose State University. Rohan Parab holds a 2014 - 2016 San Jose State University. With a robust skill set that includes Cadence Virtuoso, Linux, Field Programmable Gate Arrays Fpga, Debugging, System On A Chip Soc and more. Rohan Parab has 3 emails and 2 mobile phone numbers on RocketReach.
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