Roger Carpenter Email & Phone Number
Physical Design Manager @ Google
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Roger Carpenter Location
- San Francisco, CA, US
Roger Carpenter Work
- Physical Design Manager @ (April 2018 - Present)
- VP Design Methodology @ (February 2010 - March 2018)
- Vice President, Design and Services @ Envis (May 2009 - February 2010)
- Chief Technology Officer @ Javelin Design Automation (July 2008 - May 2009)
- Vice President, Strategic Technology @ (March 2004 - July 2008)
- Senior Manager, Design Implementation @ (July 2000 - March 2004)
- Director of Design Services @ (June 1998 - July 2000)
- Engineering Manager, Microprocessor, Circuit, and Physical Design @ (January 1994 - January 1998)
- Senior Integrated Circuit Design Engineer @ (January 1991 - January 1994)
- Solid State Device Engineer @ National Semiconductor (August 1989 - March 1991)
- Research Assistant @ MIT Submicron Structures Laboratory (December 1987 - May 1989)
- Circuit Engineer @ Fairchild Semiconductor (May 1986 - August 1987)
- Software Engineer @ (May 1985 - August 1985)
Roger Carpenter Education
- Massachusetts Institute of Technology
Master of Science (M.S.) (Electrical Engineering and Computer Science)
1987-1989 - Massachusetts Institute of Technology
Bachelor of Science (BS) (Electrical Engineering and Computer Science)
1984-1988
Roger Carpenter Skills
- ARM
- ASIC
- Algorithms
- Analog
- Analog Circuit Design
- C
- CMOS
- Cadence
- Cadence Virtuoso
- Circuit Design
- Computer Architecture
- DFT
- Debugging
- Digital Signal Processors
- EDA
- Electrical Engineering
- Embedded Systems
- FPGA
- Firmware
- Formal Verification
- Functional Verification
- Hardware Architecture
- IC
- Integrated Circuit Design
- Logic Synthesis
- Low-power Design
- Microprocessors
- Mixed Signal
- ModelSim
- Perl
- Physical Design
- Power Management
- Processors
- RTL design
- SPICE
- Semiconductor Industry
- Semiconductors
- Sensors
- Signal Integrity
- Silicon
- Simulations
- SoC
- Static Timing Analysis
- SystemC
- SystemVerilog
- TCL
- Timing Closure
- VHDL
- VLSI
- Verilog
- Integrated Circuit
- C++
- Design
- Low Power Design
- Digital Signal
Roger Carpenter Summary
- Roger Carpenter, based in San Francisco, CA, US, is currently a Physical Design Manager at Google. Roger Carpenter brings experience from previous roles at Wave Computing, Envis, Javelin Design Automation and Magma Design Automation. Roger Carpenter holds a 1987 - 1989 Master of Science (M.S.) in Electrical Engineering and Computer Science @ Massachusetts Institute of Technology. With a robust skill set that includes ARM, ASIC, Algorithms, Analog, Analog Circuit Design and more. Roger Carpenter has 5 emails and 2 mobile phone numbers on RocketReach.
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