Robert Eilers Email & Phone Number
Sr. Director Silicon Engineering @ Microsoft
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Robert Eilers Location
- Beaverton, OR, US
Robert Eilers Work
- Sr. Director Silicon Engineering @ (September 2024 - Present)
- Principal Technical Program Manager @ (June 2022 - September 2024)
- Manager - Power Solutions IP Structural Design Team @ (December 2021 - June 2022)
- Project Design Lead - Power Systems IP @ (December 2019 - January 2022)
- Manager - Modular Die I and O Front End Team @ (October 2018 - December 2019)
- Manager - Multi-Chip IO Pre-Si Verification Team @ (July 2015 - October 2018)
- Staff Component Design Engineer @ (July 2010 - July 2015)
- Staff Electrical Design Engineer @ Cypress Semiconductor (September 2005 - July 2010)
- Senior Electrical Design Engineer @ Cypress Semiconductor (January 2003 - September 2005)
- Product and Test Engineer @ Cypress Semiconductor (July 2001 - January 2003)
- Intern @ UPS Aviation Technologies (April 2000 - September 2000)
Robert Eilers Education
- Portland State University
M.S.
2006-2009 - Oregon State University
B.S
1997-2001
Robert Eilers Skills
- ASIC
- Analog
- Application-Specific Integrated Circuits (ASIC)
- CMOS
- Cadence ICFB
- Cadence Schematic Capture
- Cadence Virtuoso
- Computer Architecture
- Debugging
- Electrical Engineering
- Functional Verification
- IC
- Integrated Circuit Design
- Integrated Circuits (IC)
- Logic Design
- Management
- Microcontrollers
- Mixed Signal
- Mixed-Signal IC Design
- Nanosim
- OVM
- Open Verification Methodology
- PCB Design
- PCIe
- PLL
- Product Engineering
- RTL Design
- Semiconductors
- Silicon
- Simulations
- Synopsys tools
- System on a Chip (SoC)
- Team Management
- Testing
- Transistors
- VLSI
- Validation
- Verilog
- Verilog-A
- Verilog-AMS
- Very-Large-Scale Integration (VLSI)
- Xa
- Leadership
- Research
- Application Specific Integrated Circuits Asic
- Integrated Circuits Ic
- Integrated Circuit
- Customer Service
- Verilog Ams
- Cadence Schematic
- System on a Chip Soc
- Very Large Scale Integration Vlsi
- PowerPoint
- Microsoft Office
- Mixed Signal Ic Design
- Integrated Circuits
- System on a Chip
- Application Specific Integrated Circuits
- Very Large Scale Integration
Robert Eilers Summary
- Robert Eilers, based in Beaverton, OR, US, is currently a Sr. Director Silicon Engineering at Microsoft. Robert Eilers brings experience from previous roles at Microsoft and Intel Corporation. Robert Eilers holds a 2006 - 2009 M.S. @ Portland State University. With a robust skill set that includes ASIC, Analog, Application-Specific Integrated Circuits (ASIC), CMOS, Cadence ICFB and more. Robert Eilers has 2 emails and 2 mobile phone numbers on RocketReach.
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